1. Field of the Invention
Embodiments of the present invention relate generally to memory devices and, more particularly, in one or more embodiments, to adjusting erase voltages in memory devices.
2. Description of the Related Art
Processor-based systems, such as computers, typically include one or more memory devices to provide storage capability for the system. System memory is generally provided in the form of one or more integrated circuit chips or devices and generally includes both random access memory (RAM) and read-only memory (ROM). System RAM is typically large and volatile and provides the system's main memory. Static RAM and Dynamic RAM are commonly employed types of random access memory. In contrast, system ROM is generally small and includes non-volatile memory for storing initialization routines and identification information. Electrically-erasable read only memory (EEPROM) is one commonly employed type of memory, wherein an electrical charge may be used to program and/or erase data in the memory.
One type of non-volatile memory that is of particular use is a flash memory. A flash memory is a type of EEPROM that can be erased and reprogrammed in blocks. Flash memory is often employed in personal computer systems in order to store the Basic Input Output System (BIOS) program such that it can be easily updated. Flash memory is also employed in wireless electronic devices, because it enables the manufacturer to support new communication protocols as they become standardized and provides the ability to remotely upgrade the device for enhanced features.
Flash memory includes a memory array having a large number of memory cells arranged in “rows” and “columns”. The memory cells are generally grouped into pages which may be programmed simultaneously. Additionally, the pages are grouped into blocks and the cells within a block may all be erased simultaneously. Each of the memory cells includes a memory cell with a charge storage node, such as a floating-gate field-effect transistor capable of holding a charge. Other charge storage nodes could include, for example, charge trapping layers and the like. Floating gate memory cells differ from standard MOSFET designs in that they include an electrically isolated gate, referred to as the “floating gate,” in addition to the standard control gate. The floating gate is generally formed over the channel and separated from the channel by a gate oxide. The control gate is formed directly above the floating gate and is separated from the floating gate by another thin oxide layer. A floating gate memory cell stores information by holding electrical charge within the floating gate. By adding or removing charge from the floating gate, the threshold voltage of the cell changes, thereby defining whether this memory cell is programmed or erased.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected to a select line, which is often referred to as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a transfer line, which is often referred to as a bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the bit line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the bit lines.
As mentioned above, memory cells may be programmed on a page basis and erased on a block basis. However, memory cells adjacent to the select gates (referred to as “edge memory cells”) have shown slower program and erase times than other memory cells. This is due in part to the edge cells having a low coupling ratio with the source or drain select gates to which they are adjacent and a higher coupling ratio with the substrate. Additionally, the coupling ratio of the edge memory cells with the select gates is inconsistent due to misalignment between the memory cells. The misalignment occurs during processes commonly used to manufacture the floating gate memory devices. Additionally, where blocks are manufactured in block pairs, i.e., even and odd blocks, is the misalignment is generally different between the first block and the second block of the block pair. The variance in program and erase times caused by the misalignment of the memory cells is generally undesirable.
Embodiments of the present invention may be directed to one or more of the problems set forth above.